;/*		SCRAMmer V37.3 - 28th July 1992
;**		-------------------------------
;**
;**		Copyright (c)
;**			Giuliano C. Peritore
;**			Via Amaseno, 6
;**			04100 Latina
;**			ITALY
;**
;**			Phone: (+39) 773 491692 Voice Only
;**
;**			EMAIL mc6040@mclink.it
;*/

	SECTION	"Fast",CODE

	XDEF	_PassVBR	;Execute Pass/Set in Disable()
	XDEF	_SetVBR		;Call via Supervisor()
	XDEF	_ReadVBR	;Call via Supervisor()
	XDEF	_RefreshRate	;Execute in Disable()
	XDEF	_PageDetectOn	;Execute in Disable()
	XDEF	_PageDetectOff	;Execute in Disable()
	XDEF	_BurstOn	;Execute in Disable()
	XDEF	_BurstOff	;Execute in Disable()
	XDEF	_WrapOn		;Execute in Disable()
	XDEF	_WrapOff	;Execute in Disable()
	XDEF	_ReadRamsey
	XDEF	_SetBERR
	XDEF	_SetDSACK
	XDEF	_TimeoutOn
	XDEF	_TimeoutOff
	XDEF	_Timeout
	XDEF	_TOEnabled
	XDEF	_DetectCold
	XDEF	_SetKBRSTEN
	XDEF	_UnsetKBRSTEN
	XDEF	_DetectKBRSTEN
	XDEF	_GaryID		;Execute in Disable()
	XDEF	_RamseyID
	XDEF	_AgnusID
	XDEF	_DeniseID
	XDEF	_DoTimeout
	XDEF	_RamTestR
	XDEF	_RamTestW
	XDEF	_Block
	XDEF	_UnBlock
	XDEF	_TestChipInFast	;Execute in Disable()
	XDEF	_TestDMAC		;Ececute in Disable()

CYCLES	EQU	$00002000

DMAC	EQU	$00dd0004	;DMAC
DENISEID	EQU	$00dff07c	;Denise
VPOSR		EQU	$00dff004	;Agnus
TIMEOUT		EQU	$00de0000	;Gary
TOENB		EQU	$00de0001	;Gary
COLDSTART	EQU	$00de0002	;Gary
GARYID		EQU	$00de1002	;Gary
KBRSTEN		EQU	$00de1001	;Gary
RAMSEY		EQU	$00de0003	;Ramsey
RAMSEYID	EQU	$00de0043	;Ramsey
DMACON		EQU	$00dff096
INTENA		EQU	$00dff09a
vbrtemp:	dc.l	0	;Temporary storage for VBR

;/*------------------------------------------------------------------*/
_PassVBR:
	lea	vbrtemp(pc),a0
	move.l	4(a7),(a0)
	rts
;/*------------------------------------------------------------------*/
_SetVBR:
	move.l	vbrtemp(pc),d0
	dc.l	$4e7b0801	;MOVEC d0,VBR
	rte
;/*------------------------------------------------------------------*/
_ReadVBR:
	dc.l	$4e7a0801	;MOVEC VBR,d0
	rte
;/*------------------------------------------------------------------*/
_RefreshRate:
	move.l	4(a7),d0
	and.b	#%00000011,d0
	lsl.b	#5,d0
	move.b	RAMSEY,d1
	and.b	#%10011111,d1
	or.b	d0,d1
	move.b	d1,RAMSEY
	and.b	#%01100000,d1
1$	move.b	RAMSEY,d0
	and.b	#%01100000,d0
	cmp.b	d0,d1
	bne.s	1$
	rts
;/*------------------------------------------------------------------*/
_PageDetectOn:
	move.b	RAMSEY,d0
	ori.b	#%00000001,d0
	move.b	d0,RAMSEY
1$	move.b	RAMSEY,d0
	btst	#0,d0
	beq.s	1$
	rts
;/*------------------------------------------------------------------*/
_PageDetectOff:
	move.b	RAMSEY,d0
	and.b	#%11111110,d0
	move.b	d0,RAMSEY
1$	move.b	RAMSEY,d0
	btst	#0,d0
	bne.s	1$
	rts
;/*------------------------------------------------------------------*/
_BurstOn:
	move.b	RAMSEY,d0
	ori.b	#%00000010,d0
	move.b	d0,RAMSEY
1$	move.b	RAMSEY,d0
	btst	#1,d0
	beq.s	1$
	rts
;/*------------------------------------------------------------------*/
_BurstOff:
	move.b	RAMSEY,d0
	and.b	#%11111101,d0
	move.b	d0,RAMSEY
1$	move.b	RAMSEY,d0
	btst	#1,d0
	bne.s	1$
	rts
;/*------------------------------------------------------------------*/
_WrapOn:
	move.b	RAMSEY,d0
	ori.b	#%00000100,d0
	move.b	d0,RAMSEY
1$	move.b	RAMSEY,d0
	btst	#2,d0
	beq.s	1$
	rts
;/*------------------------------------------------------------------*/
_WrapOff:
	move.b	RAMSEY,d0
	and.b	#%11111011,d0
	move.b	d0,RAMSEY
1$	move.b	RAMSEY,d0
	btst	#2,d0
	bne.s	1$
	rts
;/*------------------------------------------------------------------*/
_ReadRamsey:
	moveq	#0,d0
	move.b	RAMSEY,d0
	rts
;/*------------------------------------------------------------------*/
_SetBERR:
	move.b	#$80,TIMEOUT
	rts
;/*------------------------------------------------------------------*/
_SetDSACK:
	move.b	#$00,TIMEOUT
	rts
;/*------------------------------------------------------------------*/
_TimeoutOn:
	move.b	#$00,TOENB
	rts
;/*------------------------------------------------------------------*/
_TimeoutOff:
	move.b	#$80,TOENB
	rts
;/*------------------------------------------------------------------*/
_Timeout:
	moveq	#0,d0
	move.b	TIMEOUT,d0
	and.b	#$80,d0
	rol.b	#1,d0
	rts
;/*------------------------------------------------------------------*/
_TOEnabled:
	moveq	#0,d0
	move.b	TOENB,d0
	and.b	#$80,d0
	rol.b	#1,d0
	eor.b	#$01,d0
	rts
;/*------------------------------------------------------------------*/
_DetectCold:
	moveq	#0,d0
	move.b	COLDSTART,d0
	and.b	#$80,d0
	rol.b	#1,d0
	rts
;/*------------------------------------------------------------------*/
_DetectKBRSTEN
	moveq	#0,d0
	move.b	KBRSTEN,d0
	and.b	#$80,d0
	rol.b	#1,d0
	rts
_SetKBRSTEN
	move.b	KBRSTEN,d0
	bset	#7,d0
	move.b	d0,KBRSTEN
	rts
_UnsetKBRSTEN
	move.b	KBRSTEN,d0
	bclr	#7,d0
	move.b	d0,KBRSTEN
	rts
;/*------------------------------------------------------------------*/
_GaryID:
	move.l	d2,-(a7)
	moveq	#0,d0		;Clear return value
	lea	GARYID,a0
	move.b	#$00,(a0)	;Start read operation
	moveq	#7,d2		;Read 8 bits
1$	move.b	(a0),d1		;Take value
	and.b	#$80,d1		;Get oly MSB
	or.b	d1,d0		;Store
	rol.b	#1,d0		;Adjust position for MSB first
	dbf	d2,1$		;Loop
	move.l	(a7)+,d2
	rts
;/*------------------------------------------------------------------*/
_RamseyID:
	moveq	#0,d0
	move.b	RAMSEYID,d0
	rts
;/*------------------------------------------------------------------*/
_AgnusID:
	move.w	VPOSR,d0
	and.l	#$00007f00,d0
	lsr.w	#8,d0
	rts
;/*------------------------------------------------------------------*/
_DeniseID:
	move.w	DENISEID,d0
	and.l	#$000000ff,d0
	rts
;/*------------------------------------------------------------------*/
_DoTimeout:
	move.l	$08000000,d0
	move.l	$0c000000,d0
	rts
;/*------------------------------------------------------------------*/
_RamTestR:
	move.l	4(a7),a0	;Get address to test
	move.l	(a0),-(a7)	;Preserve memory
	move.l	4(a0),-(a7)	;Preserve memory
	move.l	8(a0),-(a7)	;Preserve memory
	move.l	12(a0),-(a7)	;Preserve memory

	move.l	#$01010101,(a0)
	cmp.l	#$01010101,(a0)
	bne.s	8$
	move.l	#$10101010,(a0)
	cmp.l	#$10101010,(a0)
	bne.s	8$

	move.l	#CYCLES,d1
1$	move.l	(a0),d0
	move.l	4(a0),d0
	move.l	8(a0),d0
	move.l	12(a0),d0
	subq.l	#1,d1
	bne	1$

	move.l	#CYCLES,d1
2$	move.l	1(a0),d0
	move.l	3(a0),d0
	move.b	1(a0),d0
	move.b	3(a0),d0
	subq.l	#1,d1
	bne	2$

8$	move.l	(a7)+,12(a0)	;Restore memory
	move.l	(a7)+,8(a0)	;Restore memory
	move.l	(a7)+,4(a0)	;Restore memory
	move.l	(a7)+,(a0)	;Restore memory
	rts
;/*------------------------------------------------------------------*/
_RamTestW:
	move.l	4(a7),a0	;Get address to test
	move.l	(a0),-(a7)	;Preserve memory
	move.l	4(a0),-(a7)	;Preserve memory
	move.l	8(a0),-(a7)	;Preserve memory
	move.l	12(a0),-(a7)	;Preserve memory

	move.l	#$01010101,(a0)
	cmp.l	#$01010101,(a0)
	bne.s	8$
	move.l	#$10101010,(a0)
	cmp.l	#$10101010,(a0)
	bne.s	8$

	move.l	#CYCLES,d1
1$	move.l	d0,(a0)		;WRITE
	move.l	d0,4(a0)
	move.l	d0,8(a0)
	move.l	d0,12(a0)
	subq.l	#1,d1
	bne	1$

	move.l	#CYCLES,d1
2$	move.l	d0,1(a0)	;WRITE
	move.l	d0,3(a0)
	move.b	d0,1(a0)
	move.b	d0,3(a0)
	subq.l	#1,d1
	bne	2$

8$	move.l	(a7)+,12(a0)	;Restore memory
	move.l	(a7)+,8(a0)	;Restore memory
	move.l	(a7)+,4(a0)	;Restore memory
	move.l	(a7)+,(a0)	;Restore memory
	rts
;/*------------------------------------------------------------------*/
_Block
	move.w	#$0200,DMACON	;Disable DMA
	move.w	#$4000,INTENA	;Disable Ints
	rts
_UnBlock:
	move.w	#$c000,INTENA	;Enable Ints
	move.w	#$8200,DMACON	;Enable DMA
	rts
;/*------------------------------------------------------------------*/
_TestChipInFast:
	move.w	#$0200,DMACON	;Disable DMA
	move.l	4(a7),a0			;Get Address
	move.l	8(a7),d0			;Get Size
	move.l	12(a7),d1		;Get Mask (0x00000f00)
	movem.l	d2-d3,-(a7)

cyc:
	move.l	(a0),d3			;Preserve memory contents
	move.l	d1,(a0)			;Write mask
	move.l	(a0),d2			;Read val
	and.l		d1,d2				;mask it
	cmp.l		d2,d1				;Check
	bne.s		err
	clr.l		(a0)				;Clear bits
	move.l	(a0),d2			;Read val
	and.l		d1,d2				;mask result
	tst.l		d2					;Check
	bne.s		err
	move.l	d3,(a0)+
	subq.l	#4,d0
	bne.s		cyc
	moveq		#0,d0
	bra		ex

err:
	move.l	d3,(a0)			;Restore location
	move.l	a0,d0
	bra	ex

ex:
	movem.l	(a7)+,d2-d3
	move.w	#$8200,DMACON	;Enable DMA
	rts
_TestDMAC:
	move.l	#$00000004,DMAC
	move.l	DMAC,d0
	and.l		#$00000004,d0
	lsr.l		#2,d0
	rts